OpenAI reports custom inference chip matches top Nvidia processors

Benchmark results for the Jalapeño processor suggest automated design could speed up the cycle of creating specialized hardware to run artificial intelligence models.

Running modern artificial intelligence systems requires immense computing power, a demand that has made specialized silicon the central resource of the technology sector. For decades, developing a new microchip has required years of careful engineering, with teams of human designers mapping billions of microscopic connections and testing them for errors before sending blueprints to a semiconductor foundry.

When an artificial intelligence system processes a user prompt and calculates an answer, it performs a task known as inference. The efficiency and speed of that calculation decide how practical and affordable it is to run software models at large scale, leaving most developers dependent on a small group of dominant chipmakers.

On August 26, 2026, OpenAI announced benchmark performance results for an internally developed inference processor named Jalapeño, stating that the chip achieves operating speeds competitive with the top hardware produced by Nvidia, according to an announcement reported by Reed Albergotti for Semafor.¹ The development marks an effort by the research organization to build its own physical computing infrastructure.

How can software speed up hardware engineering?

Engineering a modern microchip requires two demanding stages: laying out the physical pathways of the circuit and verifying that billions of logical components function without failure. In conventional hardware development, human engineers spend years drafting these circuit layouts and running automated checks to catch design flaws before manufacturing begins.

OpenAI bypassed much of that traditional timeline by deploying its own artificial intelligence models to assist with the layout design and logic verification phases.¹ By allowing software to automate the testing and refinement of the circuit blueprints, the organization completed the development process in record time, according to reporting by Semafor.¹

This method creates a technical feedback loop. When developers use existing software models to design faster specialized processors, those finished chips can then run larger models, which in turn assist in engineering the next generation of hardware.

What do the benchmark results show?

Benchmark measurements released by OpenAI indicate that the Jalapeño processor operates at speeds rivaling the best inference chips sold by Nvidia.¹ The released figures focus specifically on inference workloads, measuring how quickly the silicon can calculate responses once a neural network has finished its initial training.

Designing the logical blueprints in-house does not eliminate the need for specialized semiconductor partners. OpenAI worked alongside Broadcom to turn the chip design into physical silicon blueprints, according to Semafor.¹ For actual fabrication, OpenAI continues to rely on commercial contract foundries, such as Taiwan Semiconductor Manufacturing Company, to manufacture the physical wafers.¹

The benchmark data represents an internal evaluation of compute performance rather than an independent third-party audit across diverse production workloads. How the chip performs when deployed in data centers alongside existing commercial infrastructure remains to be demonstrated outside of benchmark settings.

What bottlenecks remain for custom chips?

Physical constraints across the wider semiconductor supply chain limit how quickly new processor designs can translate into widespread computing capacity. Even when circuit layouts are generated rapidly by software, every manufacturer remains dependent on access to advanced memory components, vast electrical power supplies, and scarce cleanroom capacity at a handful of global fabrication plants.

These manufacturing and infrastructure hurdles mean that faster design cycles alone cannot resolve physical shortages of specialized fabrication equipment or high-bandwidth memory chips. The market will need time to expand fabrication capacity and electrical grid access before custom silicon can be deployed at scale, Semafor reported.¹

If automated circuit design proves reliable over successive chip generations, smaller engineering organizations may gain the ability to challenge established hardware giants by compressing multi-year development timelines into shorter cycles. For now, the benchmark findings show that software tools are beginning to influence physical hardware engineering as directly as they have shaped digital software development.

This piece was prepared from reporting published by Semafor and public records; the developers have not been interviewed.

References

This article is based on 1 source, listed in the order they are cited.

1. 1 RA Reed Albergotti announcement · 26 Aug 2026 OpenAI says its AI chip rivals Nvidia in inference See the source