Nobel Prize winner John Martinis shares roadmap to million-qubit supercomputers

A 92-page blueprint from 51 researchers argues that superconducting quantum computing must adopt industrial semiconductor manufacturing to reach fault tolerance.

Superconducting quantum computing will require an overhaul of hardware manufacturing and cryogenic control before large-scale machines can run practical commercial algorithms, according to a technical roadmap published by a consortium of academic institutions, government laboratories, and semiconductor firms.¹² The 92-page blueprint, authored by 51 researchers across 16 institutions, outlines the engineering milestones necessary to scale processors from hundreds of physical qubits to multi-million-qubit supercomputers capable of fault-tolerant calculation.¹³

In an interview with Primary, John Martinis, chief technology officer at Qolab and co-author of the roadmap, said the quantum hardware industry has reached a point where isolated laboratory demonstrations can no longer drive meaningful progress.⁴² Martinis, who previously led the hardware team that demonstrated quantum supremacy at Google, argued that scaling up requires transitioning from bespoke experimental assemblies to standard 300-millimeter semiconductor manufacturing lines.²³

The central hurdle facing existing superconducting architectures is the physical and electrical bottleneck created by individual coaxial cables, separate microwave components, and hand-fastened connectors.⁴³ In current dilution refrigerators, technicians manually route wiring for each physical qubit, a practice that becomes physically impossible when moving toward systems housing tens of thousands or millions of quantum elements.⁴³

"If you just look at a picture of the present systems, you have all these cables and microwave components with SMA connectors and the like," Martinis told Primary. "You basically, I'm going to just say this is kind of an artisally constructed quantum bit, which is fine in the beginning. And then our view is that you need to integrate this better. And our particular vision of this is that we integrate this using wafer scale fabrication, large chips, maybe 20,000 qubits on it, with wiring using wafers and bump bonding and to get rid of all the connectors and the like."⁴

Rethinking fabrication beyond the lift-off technique

To implement this wafer-scale integration, hardware developers are shifting away from traditional university cleanroom techniques.³⁵ For decades, superconducting Josephson junctions have relied on a process known as shadow evaporation or lift-off, where patterned photoresist stencils define the submicron features of the junction.³ Martinis pointed out that the broader microelectronics industry abandoned lift-off decades ago because resist residues introduce chemical contamination and surface defects that degrade electrical performance.³

"Right now people use something called liftoff to make the tunnel junctions for the qubits, and no one in the semiconductor industry makes submicron devices with liftoff," Martinis said. "This is a very dirty process. So we've been working on doing a deposition and etch, and we've been made some progress on that."⁴

The roadmap document highlights that amorphous dielectric insulators and dirty interfaces create two-level state defects that absorb energy from qubits, causing decoherence and gate errors.²³ In place of lift-off stencils, the proposed manufacturing architecture uses standard industrial deposition and dry plasma etching, alongside window junction geometries that eliminate contaminated perimeter edges.³ Qolab, which secured a Series A investment from Applied Ventures, the venture capital branch of Applied Materials, has focused its efforts on establishing these material interfaces inside industrial fabrication equipment.⁵

Dr. Robert Visser, vice president in the Office of the CTO at Applied Materials and a co-author on the roadmap, stated in a corporate announcement that developing processes for superconducting qubits with lower error rates and tighter uniformity represents a critical step toward large-scale manufacturing.⁵² Alan Ho, chief executive officer of Qolab, noted in the same disclosure that the collaboration reflects a broader semiconductor industry effort to bring quantum computing to scale.⁵²

The packaging architecture detailed in the blueprint pairs the qubit chip with a dedicated routing layer through indium bump-bonding.³² These specialized wiring wafers employ high-density superconducting striplines designed to route as many as 92,000 signals per layer.³ By stacking the control plane directly beneath the qubit array and replacing bulky room-temperature readout electronics with on-chip Josephson photomultipliers, designers aim to compress the physical footprint inside dilution refrigerators while mitigating thermal loads.³

The statistical hazard of hero qubits

Beyond packaging hurdles, Martinis raised concerns regarding how academic and corporate laboratories benchmark hardware progress.² Quantum computing announcements frequently celebrate peak coherence times or isolated gate fidelities measured on single, exceptionally well-behaved physical elements, a practice researchers colloquially refer to as reporting hero qubits.⁴²

Martinis argued that highlighting peak numbers misrepresents the actual technological readiness of a processor, because fault-tolerant quantum error correction is fundamentally bottlenecked by its worst-performing elements.⁴³ In a topological surface code, where physical qubits are grouped into multi-qubit arrays to detect errors, a single defective qubit with a short coherence time or an elevated error rate can poison syndrome measurements across adjacent cells.²

"Whenever you build a big system, well, okay, there's something kind of curious happens in our field," Martinis said. "And that when people talk about the progress made in superconducting qubits, they tend to talk about the best qubits, which has been dubbed the hero qubits, and in fact a lot of times it's the superhero qubits, and they're good in a variety of ways. So the one thing that I've been talking about, and other people have too, is to talk at least about the average qubits. It's nice to know what the best qubits can do, but you want to talk about, let's say, what your average qubits can do."

He added that rigorous engineering demands an even stricter standard: "If you look at any highly engineered system, it tends not to be the average that inhibits you from doing something, but the worst. If you build a transistor circuit, the worst transistors tend to limit you, and that was part of the analysis that we did, is to show that if you have a range of goodness of your qubits, with some with longer coherence time, some with shorter, the shorter ones will tend to limit you in a way that you should account for."⁴

According to the roadmap analysis, physical error rates must fall reliably into the 0.01 percent to 0.1 percent band to prevent error-correction circuits from introducing more noise than they remove.² A 50-qubit processor exhibiting a 1 percent physical error rate can execute only about two layers of simultaneous quantum logic gates before an error corrupts the system, severely restricting pre-fault-tolerant algorithms.²

Closing the latency gap in real-time decoding

For a quantum computer to execute deep circuits, it must perform active quantum error correction continuously.²³ In a rotated surface code, multi-qubit stabilizer measurements generate streams of binary measurement outcomes known as syndromes.²³ A classical processor must digest these syndromes, locate the physical faults, and calculate corrective operations before the next round of logical operations begins.²³

This decoding process is subject to severe timing constraints. Martinis emphasized that classical decoders must return solutions within the microsecond domain, matching the natural coherence windows of superconducting qubits, rather than the millisecond scales frequently seen in early software simulations.

"You need to have fast decoders," Martinis said. "This is a classical computing problem, so I feel very confident that smart computer scientists and software engineers will be able to get a factor of two or three or five to make it better. So that's something that has to get worked on. And, you know, one of the interesting things is, right now there are kind of algorithmic ways to do this, but people are also looking into neural net ways to solve this problem too, which is also very interesting. And of course, given the power of GPUs these days, I think that's an interesting way to look at it."

In complementary research focusing on real-time controls, Duc Hoang of the Phil Harris Research Group at MIT examined the latency gap between physical qubit evolution and classical host processors.⁶ Hoang observed that conventional calibration loops managed by off-chip host computers introduce communication delays ranging from seconds to minutes, during which quantum processors must halt operations.⁶ Hoang proposed embedding gradient-based training and inference directly into field-programmable gate array fabric to enable sub-microsecond feedback loops, allowing control electronics to track environmental drift and charge noise without suspending computation.

The roadmap co-authors suggest coupling superconducting quantum processors to high-throughput graphics processor clusters through specialized low-latency interfaces like NVQlink, targeting round-trip syndrome decoding latencies of under 10 microseconds.⁷ Such tightly coupled classical computing clusters allow the system to ingest massive syndrome telemetry generated by millions of physical qubits without stalling execution.³

Algorithmic compilation and resource modeling

To translate abstract quantum algorithms into concrete hardware instructions, the roadmap team evaluated automated design tools capable of scheduling operations across multi-qubit surface codes.⁸ At the 2026 APS Global Physics Summit, Artur Scherer of 1QBit presented TopQAD, a design suite developed by 1QB Information Technologies that automates topological quantum architecture synthesis and hardware noise profiling.²

The framework compiles intermediate circuit representations down to multi-qubit lattice surgery schedules implemented on a core quantum processor, while optimizing multi-level magic state factories needed to execute non-Clifford logical gates.⁸ Lattice surgery coordinates operations between distinct logical qubits by merging and splitting their planar boundaries, using multi-qubit stabilizer measurements and feedforward Pauli corrections to carry out fault-tolerant operations like the CNOT gate.

A primary objective of the roadmap was establishing realistic resource estimates for utility-scale applications, rather than relying on idealized theoretical projections.² The researchers modeled the computational resources required to simulate the electronic structure of FeMoco, the iron-molybdenum cofactor responsible for biological nitrogen fixation in the nitrogenase enzyme.³ Determining the electronic ground state of FeMoco represents a long-standing challenge in chemistry that remains intractable on classical supercomputers.³⁹

The study compared three performance tiers based on physical hardware parameters and the resulting logical error suppression factor, designated Lambda:

• Baseline specifications: Operating with current state-of-the-art parameters where Lambda equals approximately 2.34, solving the FeMoco ground state requires 120 million physical qubits and an active runtime of 1.4 years.
• Target specifications: Improving gate fidelities and fabrication uniformity to achieve a Lambda of 9.3 reduces the hardware overhead to 13 million physical qubits and shortens runtime to 122 days.
• Desired specifications: Reaching ideal hardware targets with a Lambda of 18 lowers the physical requirement to 7.7 million physical qubits and completes the calculation in 97 days.

The authors calculated that superconducting architectures could complete these complex chemical simulations two to 12 times faster than competing physical implementations, such as trapped ions or neutral atoms, primarily due to the faster gate speeds native to solid-state superconducting circuits.

Heterogeneous supercomputing and probabilistic units

Rather than positioning quantum supercomputers as standalone replacements for traditional machines, the authors argue that quantum processing units will function as domain-specific coprocessors inside classical high-performance computing centers.²³ Integrating quantum processing units alongside traditional central processing units and graphics processing units allows hybrid workloads to allocate specific computational tasks to the hardware best suited for them.²⁷

Software platforms like CUDA-Q and the HPE Cray Programming Environment are being expanded to allow developers to dispatch quantum kernels directly from C++ or Fortran programs.²³ To distribute massive calculations across multiple smaller quantum processing units without incurring prohibitive classical overheads, the roadmap introduces Adaptive Circuit Knitting.³ This technique uses tensor network methods to detect low-entanglement cuts across quantum circuits, significantly lowering classical sampling penalties and facilitating distributed execution across discrete cryostats linked by optical or capacitive networks.³

The authors also propose integrating Probabilistic Processing Units as a third computational pillar.³ Built around probabilistic bits, or p-bits, these specialized accelerators execute high-speed stochastic sampling for classical optimization and machine learning problems that lack a quantum sign problem.³ In physical models like the two-dimensional transverse-field Ising model, probabilistic processors can rapidly sample ground states within restricted Boltzmann machines, reserving full quantum hardware for sign-problematic regions.

The industrial economics of scale

The financial barrier to building large-scale quantum computers is closely linked to packaging complexity. Under current manufacturing and assembly practices, where each qubit requires dedicated microwave cabling, attenuators, and manual assembly, Martinis estimated that constructing a million-qubit system would cost tens of billions of dollars.³

"In my view, the cost per qubit is kind of a bad metric in the sense that it's all fixed costs," Martinis said. "What you want to do is talk about the cost of the whole qubit system. You have the qubit, you have various microwave devices around that, you have coax wires, lots and lots of things. If you go through the cost of using the present technology to build a million qubits, that's in the, let's say, tens of billions of dollars, which is just way too expensive."⁴

Martinis asserted that standard foundry manufacturing can alter the cost curve: "We think by integrating it in the way we're doing it, when you're mass producing, you're just sending wafers through a semiconductor kind of foundry. And then you can bring the costs down to the millions of dollars or maybe tens of millions of dollars for a big computer. That's the cost of supercomputers these days."

Following its Series B funding round, Qolab has focused on fabricating and measuring its multi-layer wiring wafers, working with external foundry partners to validate scalable interconnects.⁴ While Martinis noted that the company keeps proprietary manufacturing recipes internal, he stated that the team plans to present updated experimental measurements at international physics conferences.

When asked about the earliest commercially viable use cases for quantum computing, Martinis pointed to materials science and molecular modeling over cryptographic applications. Although breaking public-key cryptographic protocols like RSA or elliptic curves is theoretically straightforward on a fault-tolerant system, Martinis dismissed code breaking as an undesirable commercial objective due to the systemic risks it poses to internet infrastructure.⁴

"I'm more interested in doing something useful," Martinis said. "I'm interested in kind of materials and chemistry simulations. When people work on these kind of problems, they spend a lot of money, let's say for drug discovery, and if you can speed that up by a small amount, that's quite useful. That's what I'm hoping it gets used for."⁴

The transition from artisanal laboratory prototypes to factory-fabricated quantum supercomputers will depend on treating qubit development as an industrial systems engineering discipline.²³ By replacing bespoke wiring with 300-millimeter wafer packaging, enforcing strict fabrication uniformity, and connecting processors directly into classical supercomputing centers, researchers aim to turn quantum hardware from an experimental curiosity into an operational reality.³

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The record

65 sentences trace to 9 sources.

All 9Documents 4Records 1Reporting 4People 0

1. 1 A arXiv Paper · arxiv.org · 8 Sep 2026 How to Build a Quantum Supercomputer: Scaling from Hundreds to Millions of Qubits Preprint · may not have been peer reviewed See the source
2. 2 A arXiv Paper · ar5iv.labs.arxiv.org · 7 Aug 2026 How to Build a Quantum Supercomputer: Scaling from Hundreds to Millions of Qubits Preprint · may not have been peer reviewed See the source
3. 3 A arXiv Third-party reporting · alphaxiv.org · 8 Sep 2026 How to Build a Quantum Supercomputer: Scaling from Hundreds to Millions of Qubits See the source
4. 4 S Other sources Document · Other sources · 12 Oct 2026 John <> Primary News Team Not published online
5. 5 B biospace.com Third-party reporting · biospace.com · 17 Mar 2025 Qolab Secures Investment from Applied Ventures and Announces Collaboration to Advance Quantum Computing Manufacturing See the source
6. 6 A alphaXiv Document · alphaxiv.org · 2 Feb 2026 Position: The Need for Ultrafast Training See the source
7. 7 CF Center for Strategic and International Studies Third-party reporting · csis.org Pioneering Quantum-Supercomputing Integration: U.S. Leadership in the Next Computing Era See the source
8. 8 M meetings-archive.aps.org Third-party reporting · meetings-archive.aps.org Automated Design, Compilation, and Performance Benchmarking for Fault-Tolerant Quantum Computer Architectures Using TopQAD - APS Global Physics Summit 2026 See the source
9. 9 N news.fnal.gov Official record · news.fnal.gov · 25 Sep 2026 DOE releases national quantum computing roadmap following field-wide effort led by SCAC subcommittee See the source

Also consulted: 3 pages across 3 sites, none cited.

Article history

1. Update 27 Oct 2026, 18:06

   This article was updated to reflect revised text and images.

2. Published 27 Oct 2026, 18:03
   Assembled by the Primary desk from 9 sources · 65 cited sentences